This invention relates to a shift amount calculating circuit for use in a floating-point arithmetic unit for performing floating-point arithmetic of first and second input data, each of which is represented by a floating-point representation.
In the manner well known in the art, a floating-point arithmetic unit is used in performing floating-point arithmetic of first and second input data. The floating-point arithmetic may be floating-point addition, floating-point subtraction, or the like. The first and the second input data are composed of first and second exponent parts and first and second mantissa parts. Each of the first and the second mantissa parts is N bits long, where N represents a first predetermined natural number which is greater than 2.sup.n-1 and is not greater than 2.sup.n, where n represents a predetermined positive integer. Each of the first and the second exponent parts in M bits long, where M represents a second predetermined natural number which is greater than the predetermined positive integer plus one.
In general, the floating points of the first and the second mantissa parts are equalized or aligned, on performing the floating-point addition/subtraction. For this purpose, the floating-point arithmetic unit includes a shift amount calculating circuit for calculating a shift amount required for such equalization. The shift amount consists of first and second right-shift amounts for use in rightwards shifting the first and the second mantissa parts, respectively.
In the manner which will later be described, a conventional shift amount calculating circuit comprises first and second exponent subtracters, an exponent comparator, first and second selector, and first and second registers. Each of the first and the second exponent subtracters is supplied with all M bits of the first and the second exponent parts. The M bits of the first and the second exponent parts are representative of first and second numbers, respectively. The first exponent subtracter subtracts the first number from the second number to produce a first difference signal representative of a first result of subtraction. The second exponent subtracter subtracts the second number from the first number to produce a second difference signal representative of a second result of subtraction. The exponent comparator is also supplied with all M bits of the first and the second exponent parts. The exponent comparator compares the M bits of the first exponent part with the M bits of the second exponent part to produce a comparison result signal indicative of a result of comparison.
The first selector is connected to the first exponent subtracter and the exponent comparator and is supplied with a value signal indicative of a shift amount of zero. Responsive to the comparison result signal, the first selector selects one of the first difference signal and the value signal to produce a first selected signal. The second selector is connected to the second exponent subtracter and the exponent comparator and is supplied with the value signal. Responsive to the comparison result signal, the second selector selects one of the second difference signal and the value signal as a second selected signal. The first and the second registers are connected to the first and the second selectors, respectively. The first register holds the first selected signal as a first held signal to produce the first held signal as a first right-shift amount signal, which indicates the first right-shift amount. The second register holds the second selected signal as a second held signal to produce the second held signal as a second right-shift amount signal, which indicates the second right-shift amount.
In the conventional shift amount calculating circuit, each of the first and the second exponent subtracters must carry out subtraction operation on all M bits of the first and the second exponent parts. As well known in the art, an adder/subtracter includes a carry generating circuit for generating carry data. In general, the adder/subtracter carries out addition/subtraction by thus generating the carry data by the carry generating circuit and then by producing a result of addition/subtraction by the carry data. Therefore, the conventional shift amount calculating circuit comprises the first and the second exponent subtracters each of which is composed of multistage structure. This is because each of the first and the second exponent subtracters must carry out the subtraction operation on all M bits of the first and the second exponent parts. As a result, the conventional shift amount calculating circuit is disadvantageous in that each of the first and the second exponent subtracters is composed of a large amount of hardware. In addition, each of the first and the second exponent subtracters consumes much of its time in subtraction.